Last level cache (LLC) management can considerably improve the performance of Chip Multi Processors (CMPs) by reducing the miss rate and decreasing the average L1 miss latency. LLC management approaches try to either map data to caches which are closer to cores, or exploit caches of neighboring cores to increase performance and reduce off-chip misses. To reduce the miss rate, we need to use cache slices of the other cores in NUCA architectures, but it increases the average L1 miss latency since the data to be accessed by cores are located in remote cache slices. As a result, designing an intelligent management approach to improve the system performance on a variety of workloads and systems is necessary. In this paper, an adaptive cache clustering called ACC is presented. ACC augments L2 cache size by using the L2 cache slices of neighboring cores adaptively. ACC selects cache slices with minimum distance to the target core while evaluating the amount of L2 cache slices being used on the surrounding tiles. To validate our approach, we apply several applications from SPEC CPU2006 and PARSEC benchmark suites. The results show the effectiveness of our approach, as we get speedup by up to 18%.

Usually in the form of parallel processing with parallel multi-processor systems are designed. For this reason irregular flow may occur with packages. When you' re tired and it all comes out in his NP (Network Processors) system, Reset depending on network performance is negatively affected and we delayed To do this, The design of processors working in parallel packet transmission by avoiding any packet reordering occur, If reordering, this time delay is minimal. Several algorithms have been proposed in recent years. In this paper, we will describe some of the fundamental concepts involved in NP architecture and algorithms packet reordering in recent years, which causes delays are minimized packet reordering, the evaluation will be compared.

In traditional speech processing, feature extraction and classification were conducted as separate steps. The advent of deep neural networks has enabled methods that simultaneously model the relationship between acoustic and phonetic characteristics of speech while classifying it directly from the raw waveform. The first convolutional layer in these networks acts as a filter bank. To enhance interpretability and reduce the number of parameters, researchers have explored the use of parametric filters, with the SincNet architecture being a notable advancement. In SincNet's initial convolutional layer, rectangular bandpass filters are learned instead of fully trainable filters. This approach allows for modeling with fewer parameters, thereby improving the network's convergence speed and accuracy. Analyzing the learned filter bank also provides valuable insights into the model's performance. The reduction in parameters, along with increased accuracy and interpretability, has led to the adoption of various parametric filters and deep architectures across diverse speech processing applications. This paper introduces different types of parametric filters and discusses their integration into various deep architectures. Additionally, it examines the specific applications in speech processing where these filters have proven effective.

Moments are utilized in image processing for pattern recognition, machine vision and numerous feature extraction techniques. Due to computational complexity, it is difficult to use high order moments in real time processing. This paper presents the design of two new architectures for real time computation of moments, up to order 14, M00 to M77, in gray level images, based on parallel systolic arrays and pipelining technique, using a 0.18mm CMOS technology.Implementation of the moment processing element (MPE) of the first architecture illustrates a processing speed of 125 frames/s for 1024×1024 grey-level images. The maximum operating frequency and the power consumption for an architecture with 5 elements is 133 MHz and 14.36 mW, respectively. Since the design is very low power, the number of parallel MPE’s can be easily increased. Simulation shows that with 11 parallel MPE’s, the first 49 moments of 1024×1024 image are computed with the speed of 30 frames/sec.To further decrease the latency of the first architecture, the second architecture is proposed, in which the add operation is performed only with a single adder and a compressor. Simulation shows that the latency of the second architecture is 3.3 times lower than that of the first architecture. Implementation of the second architecture illustrates the maximum operating frequency and the power consumption of 125 MHz and 58.34 mW, respectively. Operating frequency and power consumption of the second architecture is approximately the same as that of the first architecture which befit real time applications.